Inverter circuit

ABSTRACT

An inverter circuit includes an IGBT ( 3 ) and an IGBT ( 4 ) connected in series between a power supply potential (Vcc) and a GND potential, and an HVIC ( 1 ) and an LVIC ( 2 ) for respectively controlling actuation of the IGBTs ( 3 ) and ( 4 ). The inverter circuit also includes a capacitor ( 5 ), a diode ( 6 ), and a resistor ( 7 ). The capacitor ( 5 ) is connected between a terminal (VS) and the GND potential. The diode ( 6 ) has a series connection to the capacitor ( 5 ) between the terminal (VS) and the GND potential, with such a polarity that a forward current flows from the GND potential to the terminal (VS). The resistor ( 7 ) is connected in parallel to the capacitor ( 5 ).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an inverter circuit.

2. Description of the Background Art

An inverter circuit generally includes high-voltage and low-voltageswitching elements connected in series between a power supply potentialand a GND potential, and high-voltage and low-voltage drive circuits forrespectively controlling actuation of the high-voltage and low-voltageswitching elements. The inverter circuit conventionally used isintroduced in Japanese Patent Application Laid-Open Nos. 2003-178895,9-219977 (1997), 10-42575 (1998), and in PCT Publication No. WO01/59918, for example.

The conventional inverter circuit faces the problem below.

At the time when the high-voltage switching element is turned off, theinverter circuit is placed in a free-wheeling mode of an FWD connectedin inverse-parallel to the low-voltage switching element (FWD of thelower arm). At this time, a negative surge voltage is generated at anoutput terminal of the inverter circuit, which voltage is the product ofdi/dt during turn-off of the high-voltage switching element and aninductance in a free-wheeling loop of the FWD of the lower arm. Thissurge voltage, when being at a predetermined level or higher, may causebreakdown or malfunction of the high-voltage drive circuit. A higherswitching current is likely to generate increase in surge voltage, thuscausing difficulty in obtaining a large current-carrying capacity of theinverter circuit.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to obtain an invertercircuit capable of suppressing a negative surge voltage resulting fromturn-off of a high-voltage switching element.

According to one aspect of the present invention, the inverter circuitincludes a high-voltage switching element and a low-voltage switchingelement, a high-voltage drive circuit, a capacitor, a diode, and aresistor. The high-voltage and low-voltage switching elements areconnected in series between a power supply potential and a GNDpotential. The high-voltage drive circuit has a terminal connected to acurrent emission terminal of the high-voltage switching element whilesupplying a reference potential of a high-potential inner circuit. Theterminal of the high-voltage drive circuit will be referred to as aterminal VS. The diode has a series connection to the capacitor betweenthe terminal VS and the GND potential, with such a polarity that aforward current flows from the GND potential to the terminal VS. Theresistor is connected in parallel either to the diode or to thecapacitor, or both.

A negative surge voltage as a result of turn-off of the high-voltageswitching element is suppressed accordingly.

According to another aspect of the present invention, the invertercircuit includes a high-voltage switching element and a low-voltageswitching element, a high-voltage drive circuit, and a diode. Thehigh-voltage and low-voltage switching elements are connected in seriesbetween a power supply potential and a GND potential. The high-voltagedrive circuit has a terminal connected to the GND potential whilesupplying a reference potential of a low-potential inner circuit. Theterminal will be referred to as a terminal COM. The diode is connectedbetween the terminal COM and the GND potential, with such a polaritythat a forward current flows form the terminal COM to the GND potential.

A negative surge voltage as a result of turn-off of the high-voltageswitching element is suppressed accordingly.

According to still another aspect of the present invention, the invertercircuit includes a high-voltage switching element and a low-voltageswitching element, a high-voltage drive circuit, and a diode. Thehigh-voltage and low-voltage switching elements are connected in seriesbetween a power supply potential and a GND potential. The high-voltagedrive circuit has a terminal connected through a bootstrap power supplycapacitor to a current emission terminal of the high-voltage switchingelement. The terminal of the high-voltage drive circuit will be referredto as a terminal VDB. The diode has a series connection to the bootstrappower supply capacitor between the current emission terminal and theterminal VDB, with such a polarity that a forward current flows from thecurrent emission terminal to the terminal VDB.

A negative surge voltage as a result of turn-off of the high-voltageswitching element is suppressed accordingly.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the configuration of an invertercircuit according to a first preferred embodiment of the presentinvention;

FIG. 2 is a circuit diagram schematically showing the configurationinside an HVIC;

FIG. 3 is a circuit diagram corresponding to FIG. 1, showing theconfiguration of an inverter circuit according to a modification of thefirst preferred embodiment;

FIG. 4 is a circuit diagram showing the configuration of an invertercircuit according to a second preferred embodiment of the presentinvention;

FIG. 5 is a circuit diagram showing the configuration inside a levelshift circuit of FIG. 2 when a diode is connected to a terminal COM ofthe HVIC;

FIG. 6 is a circuit diagram corresponding to FIG. 4, showing theconfiguration of an inverter circuit according to a third preferredembodiment of the present invention;

FIG. 7 is a circuit diagram corresponding to FIG. 4 or 6, showing theconfiguration of an inverter circuit according to a fourth preferredembodiment of the present invention;

FIG. 8 is a circuit diagram corresponding to FIG. 4 or 6, showing theconfiguration of an inverter circuit according to a fifth preferredembodiment of the present invention;

FIG. 9 is a circuit diagram corresponding to FIG. 4, showing a firstconfiguration of an inverter circuit according to a sixth preferredembodiment of the present invention;

FIG. 10 is a circuit diagram corresponding to FIG. 6, showing a secondconfiguration of the inverter circuit according to the sixth preferredembodiment;

FIG. 11 is a circuit diagram corresponding to FIG. 7, showing a thirdconfiguration of the inverter circuit according to the sixth preferredembodiment;

FIG. 12 is a circuit diagram corresponding to FIG. 8, showing a fourthconfiguration of the inverter circuit according to the sixth preferredembodiment;

FIG. 13 is a circuit diagram showing the configuration of an invertercircuit according to a seventh preferred embodiment of the presentinvention; and

FIG. 14 is a circuit diagram showing the configuration inside the levelshift circuit of FIG. 2 when a diode is connected to a terminal VDB ofthe HVIC.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

FIG. 1 is a circuit diagram showing the configuration of an invertercircuit according to a first preferred embodiment of the presentinvention. The inverter circuit is of two or more phases (generallythree phases), whereas FIG. 1 shows the configuration of a single-phasecircuit. The configuration of FIG. 1 is an extracted portion from theinverter circuit which is mainly relevant to the present invention. Theinverter circuit includes a series connection of an IGBT (high-voltageswitching element) 3 and an IGBT (low-voltage switching element) 4between a power supply potential Vcc and a GND potential, and an HVIC(high-voltage drive circuit) 1 and an LVIC (low-voltage drive circuit) 2for respectively controlling actuation of the IGBTs 3 and 4.

FIG. 2 is a circuit diagram schematically showing the configurationinside the HVIC 1. With reference to FIG. 2, the HVIC 1 includes aninput circuit, a one-shot circuit, a level shift circuit, a controlpower reduction protective circuit, and a drive circuit. Theconfiguration inside the HVIC 1 shown in FIG. 2 is common in secondthrough seventh preferred embodiments discussed later.

With reference to FIGS. 1 and 2, the HVIC 1 has terminals Vcc, PIN, COM,VDB, HO and VS. The terminal Vcc receives power to drive a low-potentialinner circuit of the HVIC 1 (including the input circuit and theone-short circuit shown in FIG. 2) from an external control power supplyVD of about 15 V. The terminal PIN receives an input signal from anexternal microcomputer. The terminal COM is connected to the GNDpotential, and serves to supply a reference potential of thelow-potential inner circuit. The terminal VDB is connected through abootstrap power supply capacitor 100 to the emitter (current emissionterminal) of the IGBT 3. The terminal HO is connected to the gate of theIGBT 3. The terminal VS is connected to the emitter of the IGBT 3, andserves to supply a reference potential of a high-potential inner circuit(including the control power reduction protective circuit and the drivecircuit shown in FIG. 2).

With reference to FIG. 1, the inverter circuit includes the bootstrappower supply capacitor 100 which is charged by the control power supplyVD when the IGBT 4 is in the on state. When the IGBT 3 is in the onstate, the bootstrap power supply capacitor 100 supplies HVIC 1 withpower to drive the high-potential inner circuit through the terminalVDB.

The inverter circuit further includes a capacitor 5, a diode 6, and aresistor 7. The capacitor 5 is connected between the terminal VS and theGND potential. The diode 6 has a series connection to the capacitor 5between the terminal VS and the GND potential, with such a polarity thata forward current flows from the GND potential to the terminal VS. Theresistor 7 is connected in parallel to the capacitor 5.

When the terminal PIN of the HVIC receives an on signal (high-levelsignal), the IGBT 3 is turned on to cause a current I1 to flow as shownin FIG. 1. When the terminal PIN thereafter receives an off signal(low-level signal), the IGBT 3 is turned off to cause a current 12 toflow as shown in FIG. 1. At the instant of flow of the current 12, anegative surge voltage is generated which is the product of di/dt duringturn-off of the IGBT 3 and an inductance in bold-lined interconnectionshown in FIG. 1.

As discussed in the description of the background art, a surge voltageat an excessive level may cause breakdown or malfunction of the HVIC 1.In response, the inverter circuit of the first preferred embodiment isallowed to suppress a surge voltage by means of a series connection ofthe capacitor 5 and the diode 6 between the terminal VS and the GNDpotential. Further, as the first preferred embodiment prevents flow of adirect current, the inverter circuit can be constituted by theinexpensive capacitor 5 and the diode 6. The first preferred embodimentstill further characteristically uses the resistor 7 to dischargeelectric charges stored in the capacitor 5 resulting from a surgevoltage, thus advantageously preventing reduction in surge absorption bythe capacitor 5.

FIG. 3 is a circuit diagram corresponding to FIG. 1, showing theconfiguration of an inverter circuit according to a modification of thefirst preferred embodiment. The configuration of FIG. 1 has a parallelconnection of the resistor 7 and the capacitor 5, whereas an alternativeconfiguration of FIG. 3 has a parallel connection of a resistor 8 andthe diode 6. Further alternatively, both the resistors 7 and 8 may beprovided. The inverter circuit shown in FIG. 3 provides the same effectas obtained by the inverter circuit of FIG. 1.

Second Preferred Embodiment

FIG. 4 is a circuit diagram showing the configuration of an invertercircuit according to a second preferred embodiment of the presentinvention. The inverter circuit is of two or more phases (generallythree phases), whereas FIG. 4 shows the configuration of a single-phasecircuit. The configuration of FIG. 4 is an extracted portion from theinverter circuit which is mainly relevant to the present invention.Instead of the capacitor 5, the diode 6 and the resistor 7 shown in FIG.1, the inverter circuit of the second preferred embodiment includes adiode 10 as an element to suppress a surge voltage resulting fromturn-off of the IGBT 3. Together with the HVIC 1, the LVIC 2, and theIGBTs 3 and 4, the diode 10 is modularized as a DIP-IPM (dual-in-linepackage intelligent power module) 9. The diode 10 has an anode connectedto the terminal COM of the HVIC 1, and a cathode connected to a terminal50 of the DIP-IPM 9. The diode 10 is provided between the terminal COMof the HVIC 1 and the GND potential, with such a polarity that a forwardcurrent flows from the terminal COM of the HVIC 1 to the GND potential.

FIG. 5 is a circuit diagram showing the configuration inside the levelshift circuit of FIG. 2 when the diode 10 is connected to the terminalCOM of the HVIC 1.

With reference to FIG. 5, when the terminal VDB is subjected toapplication of a negative surge voltage resulting from turn-off of theIGBT 3, the diode 10 serves to provide voltage clamp (reverse blocking)between the terminals COM and VDB. As a result, the second preferredembodiment causes no application of a surge voltage at an excessivelevel between the terminals COM and VDB while preventing flow of acurrent, whereby the HVIC 1 is protected from breakdown or malfunction.

Third Preferred Embodiment

FIG. 6 is a circuit diagram corresponding to FIG. 4, showing theconfiguration of an inverter circuit according to a third preferredembodiment of the present invention. In the inverter circuit of thethird preferred embodiment, the usual diode 10 shown in FIG. 4 isreplaced by a fast recovery diode 1 1 that is the same in polarity asthe diode 10.

In the inverter circuit shown in FIG. 4, the diode 10 continuouslyreceives a circuit current of the HVIC 1 supplied from the control powersupply VD. When the terminal VDB is subjected to application of theforegoing negative surge voltage (that is, when the diode 10 is reversebiased by this negative surge voltage), the surge voltage is appliedaccordingly between the terminals COM and VDB in a recovery time of thediode 10. As a result, malfunction of the HVIC 1 is likely.

In response, in the inverter circuit of the third preferred embodiment,the usual diode 10 shown in FIG. 4 is replaced by the fast recoverydiode 11. The fast recovery diode 11 requires shorter recovery time thanthe usual diode 10 and hence, application of the surge voltage betweenthe terminals COM and VDB continues for a shorter length of time,whereby enhanced malfunction capability is obtained.

Fourth Preferred Embodiment

In the inverter circuit shown in FIG. 4 or 6, identifying the voltage atthe control power supply VD as VD0, and a surge voltage applied acrossthe diode 10 or the fast recovery diode 11 as VR0, a voltage of VD0+VR0is applied between the terminals Vcc and COM of the HVIC 1. When thesurge voltage VR0 has an excessive level and thus a voltage exceeding arated voltage Vm is applied between the terminals Vcc and COM of theHVIC 1, breakdown of the HVIC 1 is likely.

FIG. 7 is a circuit diagram corresponding to FIG. 4 or 6, showing theconfiguration of an inverter circuit according to a fourth preferredembodiment of the present invention. In the inverter circuit of thefourth referred embodiment, the usual diode 10 of FIG. 4 or the fastrecovery diode 11 of FIG. 6 is replaced by a Zener diode 12 having aZener voltage Vz1 that is the same in polarity as the diode 10 or thefast recovery diode 11. The Zener voltage Vz1 of the Zener diode 12 hassuch a level that the sum of the voltages VD0 and Vz1 is not higher thanthe rated voltage Vm.

According to the inverter circuit of the fourth preferred embodiment, inthe event of application of a surge voltage at an excessive level, thevoltage between the terminals Vcc and COM of the HVIC 1 is clamped atthe voltage of VD0+Vz1 which is not higher than the rated voltage Vm. Asa result, breakage of the HVIC 1 is prevented.

Fifth Preferred Embodiment

As discussed in the fourth preferred embodiment above, when the surgevoltage VR0 has an excessive level and thus a voltage exceeding therated voltage Vm is applied between the terminals Vcc and COM of theHVIC 1, breakdown of the HVIC 1 is likely.

FIG. 8 is a circuit diagram corresponding to FIG. 4 or 6, showing theconfiguration of an inverter circuit according to a fifth preferredembodiment of the present invention. The inverter circuit of the fifthpreferred embodiment further includes a Zener diode 13 having a Zenervoltage Vz2 in addition to the usual diode 10 of FIG. 4 or the fastrecovery diode 11 of FIG. 6. The Zener diode 13 has an anode connectedto the terminal COM of the HVIC 1, and a cathode connected to theterminal Vcc of the HVIC 1. The Zener voltage Vz2 of the Zener diode 13has a level which is not higher than the rated voltage Vm between theterminals Vcc and COM of the HVIC 1.

According to the inverter circuit of the fifth preferred embodiment, inthe event of application of a surge voltage at an excessive level, thevoltage between the terminals Vcc and COM of the HVIC 1 is clamped atthe Zener voltage Vz2 which is not higher than the rated voltage Vm. Asa result, breakdown of the HVIC 1 is prevented.

Sixth Preferred Embodiment

FIG. 9 is a circuit diagram corresponding to FIG. 4, showing a firstconfiguration of an inverter circuit according to a sixth preferredembodiment of the present invention. FIG. 4 shows the single diode 10,whereas the inverter circuit actually has a configuration of two or morephases (generally three phases). The HVIC 1 and the control power supplyVD are provided in each phase. That is, the diode 10 of FIG. 4 isprovided responsive to the HVIC 1 in each phase.

In contrast, in the inverter circuit shown in FIG. 9, the terminals COMof the HVICs 1 in the respective phases are connected to each other in aDIP-IPM 15. That is, only one control power supply VD is required as acommon control power supply among the HVICs 1 in two or more phases,thus correspondingly requiring only one diode 16 as a common diode amongthe HVICs 1 in two or more phases. The diode 16 is provided outside theDIP-IPM 15. The diode 16 has an anode connected to a terminal 51 of theDIP-IPM 15, and a cathode connected to the GND potential of the controlpower supply VD. The terminal 51 is connected to the terminals COM ofthe HVICs 1.

FIG. 10 is a circuit diagram corresponding to FIG. 6, showing a secondconfiguration of the inverter circuit according to the sixth preferred.The inverter circuit of FIG. 10 includes only one fast recovery diode 17as a common diode among the HVICs 1 in two or more phases that replacesthe fast recovery diode 11 (FIG. 6) which is provided responsive to theHVIC 1 in each phase.

FIG. 11 is a circuit diagram corresponding to FIG. 7, showing a thirdconfiguration of the inverter circuit according to the sixth preferredembodiment. The inverter circuit of FIG. 11 includes only one Zenerdiode 18 as a common diode among the HVICs 1 in two or more phases thatreplaces the Zener diode 12 (FIG. 7) which is provided responsive to theHVIC 1 in each phase.

FIG. 12 is a circuit diagram corresponding to FIG. 8, showing a fourthconfiguration of the inverter circuit according to the sixth preferredembodiment. In addition to the foregoing characteristics discussed withreference to FIG. 9 or 10, the inverter circuit of FIG. 12 includes onlyone Zener diode 19 as a common diode among the HVICs 1 in two or morephases that replaces the Zener diode 13 (FIG. 8) which is providedresponsive to the HVIC 1 in each phase. The Zener diode 19 has an anodeconnected to the terminal 51 of the DIP-IPM 15, and a cathode connectedto a terminal 52 of the DIP-IPM 15 having a connection to the terminalsVcc of the HVICs 1.

The inverter circuit of the sixth preferred embodimentcharacteristically includes the diode 16, the fast recovery diode 17, orthe Zener diode 18 or 19 each serving as a common diode among the HVICs1 in two or more phases. As compared with the configuration where thesediodes are provided in each phase, the inverter circuit of the sixthpreferred embodiment realizes simpler configuration.

Seventh Preferred Embodiment

FIG. 13 is a circuit diagram showing the configuration of an invertercircuit according to a seventh preferred embodiment of the presentinvention. The inverter circuit is of two or more phases (generallythree phases), whereas FIG. 13 shows the configuration of a single-phasecircuit. The configuration of FIG. 13 is an extracted portion from theinverter circuit which is mainly relevant to the present invention.Instead of the capacitor 5, the diode 6 and the resistor 7 shown in FIG.1, the inverter circuit of the seventh preferred embodiment includes adiode 21 as an element to suppress a surge voltage resulting fromturn-off of the IGBT 3. The diode 21 is provided outside a DIP-IPM 20.The diode 21 has an anode connected to the bootstrap power supplycapacitor 100, and a cathode connected to a terminal 53 of the DIP-IPM20. The terminal 53 is connected to the terminal VDB of the HVIC 1. Thediode 21 thus has a series connection to the bootstrap power supplycapacitor 100 between the emitter of the IGBT 3 and the terminal VDB ofthe HVIC 1, with such a polarity that a forward current flows from theemitter to the terminal VDB.

FIG. 14 is a circuit diagram showing the configuration inside the levelshift circuit of FIG. 2 when the diode 21 is connected to the terminalVDB of the HVIC 1.

With reference to FIG. 14, when a negative surge voltage is applied tothe terminal VDB resulting from turn-off of the IGBT 3, a diode 30 ofFIG. 14 is forward biased to cause a current flow in the absence of thediode 21. This may interfere with level shifting to cause malfunction.In response, in the inverter circuit of the seventh preferredembodiment, the diode 21 connected to the terminal VDB serves to preventsuch a current flow. As a result, the HVIC 1 is protected frommalfunction.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1. An inverter circuit, comprising: a high-voltage switching element anda low-voltage switching element connected in series between a powersupply potential and a GND potential; a high-voltage drive circuithaving a terminal connected to a current emission terminal of saidhigh-voltage switching element while supplying a reference potential ofa high-potential inner circuit, said terminal of said high-voltage drivecircuit being referred to as a terminal VS; a capacitor connectedbetween said terminal VS and said GND potential; a diode having a seriesconnection to said capacitor between said terminal VS and said GNDpotential, with such a polarity that a forward current flows from saidGND potential to said terminal VS; and a resistor connected in paralleleither to said diode or to said capacitor, or both.
 2. An invertercircuit, comprising: a high-voltage switching element and a low-voltageswitching element connected in series between a power supply potentialand a GND potential; a high-voltage drive circuit having a terminalconnected to said GND potential while supplying a reference potential ofa low-potential inner circuit, said terminal being referred to as aterminal COM; and a diode connected between said terminal COM and saidGND potential, with such a polarity that a forward current flows fromsaid terminal COM to said GND potential.
 3. The inverter circuitaccording to claim 2, wherein said diode is a fast recovery diode. 4.The inverter circuit according to claim 2, wherein said high-voltagedrive circuit includes a plurality of high-voltage drive circuits,wherein said plurality of high-voltage drive circuits are provided inrespective phases of said inverter circuit, wherein said terminals COMof said plurality of high-voltage drive circuits are connected to eachother, and wherein said diode is a common diode among said plurality ofhigh-voltage drive circuits.
 5. The inverter circuit according to claim2, wherein said high-voltage drive circuit further has a terminal forreceiving power to drive said low-potential inner circuit, said terminalfor receiving said power being referred to as a terminal Vcc, saidinverter circuit further comprising a Zener diode having an anodeconnected to said terminal COM, and a cathode connected to said terminalVcc.
 6. The inverter circuit according to claim 5, wherein saidhigh-voltage drive circuit includes a plurality of high-voltage drivecircuits, wherein said plurality of high-voltage drive circuits areprovided in respective phases of said inverter circuit, wherein saidterminals COM of said plurality of high-voltage drive circuits areconnected to each other, and wherein said diode and said Zener diode areeach a common diode among said plurality of high-voltage drive circuits.7. The inverter circuit according to claim 2, wherein said diode is aZener diode.
 8. The inverter circuit according to claim 7, wherein saidhigh-voltage drive circuit includes a plurality of high-voltage drivecircuits, wherein said plurality of high-voltage drive circuits areprovided in respective phases of said inverter circuit, wherein saidterminals COM of said plurality of high-voltage drive circuits areconnected to each other, and wherein said Zener diode is a common diodeamong said plurality of high-voltage drive circuits.
 9. An invertercircuit, comprising: a high-voltage switching element and a low-voltageswitching element connected in series between a power supply potentialand a GND potential; a high-voltage drive circuit having a terminalconnected through a bootstrap power supply capacitor to a currentemission terminal of said high-voltage switching element, said terminalof said high-voltage drive circuit being referred to as a terminal VDB;and a diode having a series connection to said bootstrap power supplycapacitor between said current emission terminal and said terminal VDB,with such a polarity that a forward current flows from said currentemission terminal to said terminal VDB.